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TS1103 page 1 ? 2012 touchstone semiconductor, inc. all rights reserved. features ? ultra - low supply current: 1a ? wi de input common mode range: +2 v to + 25v ? low input offset voltage: 2 0 0 v (max) ? low gain error: 0.6 % (max) ? voltage output ? four gain options available: TS1103 - 25 : gain = 25v/v TS1103 - 50 : gain = 50v/v TS1103 - 100 : gain = 100v/v TS1103 - 200 : gain = 200v/v ? 6 - lead sot23 packaging applications notebook computers power management systems portable/battery - powered systems smart chargers smart phones description the TS1103 is the latest addition to the ts1101 family of bi - directional current - sense amplifiers. consuming a very low 1a supply current, the TS1103 high - side curr ent - sense amplifiers combine a 2 0 0 - v (max) v os and a 0.6 % (max) gain error for cost - sensitive applications . for all high - side bidirectional current - sensing applications, the TS1103 s are self - powered and feature a wide input common - mode voltage range from 2 v to 25v . a sign comparator digital output is also provided that indicates the direction of current flow depending on the external connections to the TS1103 s rs+ and rs - input terminals. the sot23 package make s the TS1103 an ideal choice for pcb - area - critical, supply - current - conscious , high - accuracy current - sense applications in all battery - powered and portable instruments. all TS1103 s are specified for operation over the - 40c to +105 c extended temperature range. a 1a, 2 00 v os bidirectional precision current - sense amplifier typical application circuit part gain option TS1103 - 25 25 v/v TS1103 - 50 50 v/v TS1103 - 100 100 v/v TS1103 - 200 2 00 v/v t he touchstone semicondu c tor logo is a registered trademark of touchstone semiconductor, incorporated. sign comparator s symmetric i load crossover
TS1103 page 2 TS1103ds r1p0 rtfds absolute maximum rat ings rs+, rs - to gnd ................................ .............. - 0.3v to +27 v v dd , out , sign to gnd ................................ ....... - 0.3v to +6 rs+ to rs - ................................ ................................ ..... 27 v short - circuit duration: out to gnd .................... continuous continuous input current (any pin) ............................ 20ma continuous power dissipation (t a = +70c) 6 - lead sot23 (derate at 4.5mw/c above +70c) ................................ ................................ ............... 360 mw operating temperature range .................... - 40c to +105 c junction temperature ................................ ................ +150c storage temperature range ....................... - 65c to +150c lead temperature (soldering, 10s) ........................... +300c soldering temperature (reflow) ............................ +260c electrical and thermal s tresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional opera tion of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime . package/ordering inf ormation order number part marking carrier quantity TS1103 - 25eg6tp tad w tape & reel ----- TS1103 - 25eg6t tape & reel 3000 TS1103 - 50eg6tp tad x tape & reel ----- TS1103 - 50eg6t tape & reel 3000 TS1103 - 100eg6tp tad y tape & reel ----- TS1103 - 100eg6t tape & reel 3000 TS1103 - 200eg6tp tad z tape & reel ----- TS1103 - 200eg6t tape & reel 3000 lead - free program: touchstone semico nductor supplies only lead - free packaging. consult touchstone semiconductor for products specified with wider operating temperature ranges.
TS1103 TS1103ds r1p0 page 3 rtfds electrical character istics v rs+ = 3.6v; v sense = (v rs+ - v rs - ) = 0v; c out = 47nf; v dd = 1.8v; t a = - 40c to +105 c, unless otherwise noted. typical values are at t a = +25c. see note 1 . parameter symbol conditions min typ max units supply current (note 2) i cc t a = +25c 0.68 0.85 a 1. 0 v rs+ = 2 5 v t a = +25c 1.0 1.2 common - mode input range v cm guaranteed by cmrr 2 25 v current sense amplifier parameter s common - mode rejection ratio cmrr 2 v < v rs+ < 2 5 v 120 150 db input offset voltage (note 3) v os t a = +25c 30 2 00 v 3 00 v os hysteresis (note 4) v hys t a = +25c 10 v gain g TS1103 - 25 25 v/v TS1103 - 50 50 TS1103 - 100 100 TS1103 - 200 200 gain error (note 5) ge t a = +25c 0.2 0. 6 % 1.0 gain match (note 5) gm t a = +25c 0.2 0.6 % 1 output resistance (note 6 ) r out TS1103 - 25/50/100 7.0 10 13.2 k TS1103 - 200 14.0 20 26.4 out low voltage v ao l gain = 25 5 mv gain = 50 10 gain = 100 20 gain = 200 4 0 out high voltage (note 7 ) v ao h v oh = v rs - - v out 0. 05 0.2 v output settling time t s TS1103 - 25/50/100 1% final value, v out = 3 v 2.2 m s TS1103 - 200 4.3 sign comparator parameter s vdd supply voltage range v dd 1.2 5 5.5 v vdd supply current i dd 0.02 0.2 a output low voltage v col v dd = 1.25v, i sink = 5a 0.2 v v dd = 1.8v, i sink = 35a output high voltage v co h v dd = 1.25v, i s ource = 5a v dd C 0.2 v v dd = 1.8v, i s ource = 35a propagation delay t pd v sense = 1mv 3 ms v sense = 10mv 0.4 note 1: all devices are 100% production tested at t a = +25c. all temperature limits are guaranteed by product characterization. note 2: extrapolated to v out = 0. i cc is the total current into the rs+ and the rs - pins. note 3: input offset voltage v os is extrapolated from a v out + measurement with v sense set to + 1mv and a v out - measurement with v sense set to - 1mv; vis - a - viz, average v os = v - - v + x a note 4: amplitude of v sense lower or higher than v os required to cause the comparator to switch output states. note 5 : gain error applies to current flow in either direction and is calculated by applying two values for v sense and then calculating the error of the actual slope vs. the ideal transfer characteristic: for gain = 25, the applied v sense is 20mv and 120mv. for g ain = 50, the applied v sense is 10mv and 60mv. for g ain = 100, the applied v sense is 5mv and 30mv. fo r g ain = 200, the applied v sense is 2.5mv and 15mv. note 6 : the device is stable for any capacitive load at v out . note 7 : v oh is the voltage from v rs - to v out with v sense = 3.6v/gain.
TS1103 page 4 TS1103ds r1p0 rtfds input offset voltage vs common - mode voltage supply current vs common - mode voltage input offset voltage vs temperature supply current vs temperature percent of units - % input offset voltage - v percent of units - % gain error - % input offset voltage - v temperature - c temperature - c supply curent - a supply voltage - volt 0 5 15 20 20 15 10 0 10 30 - 10 40 2v 25v 3.6v input offset voltage - v supply voltage - volt supply current - a typical performance characteristics v rs+ = v rs - = 3.6 v; t a = +25 c, unless otherwise noted. - 40 - 15 10 60 110 85 0 5 10 15 30 25 10 20 5 0.2 0.6 0.8 0 0.4 1 40 25 30 35 - 20 0 40 80 - 40 20 60 - 0.4 0.2 - 0.6 0.6 0 20 input offset voltage histogram gain error histogram 60 30 25 35 30 25 35 20 0 5 10 15 30 25 20 0.2 0.6 0.8 0 0.4 1 - 40 - 15 10 60 110 85 35 50 - 0.2 0.4 35
TS1103 TS1103ds r1p0 page 5 rtfds gain error vs common - mode voltage supply voltage - volt gain error vs. temperature small - signal gain vs frequency small - signal gain - db v sense - mv common - mode rejection - db 0 0.2 0.3 0.001 0.1 1 10 1000 5 - 5 - 15 - 35 - 25 10 20 0 30 gain error - % g = 100 g = 25 g = 50 g = 100 g = 50 g = 25 v out vs v sense @ supply = 3.6v v out - v g = 25 g = 100 g = 50 g =25 g = 50, 100 frequency - khz common - mode rejection vs frequency 0.1 - 0.3 - 0.2 0.1 0.2 0.3 - 0.1 0 15 5 0 150 100 50 0 100 60 20 0 1 2.5 3 3.5 4 1.5 2 0 0.2 0.8 1.0 2 0.4 0.6 0 - 10 - 20 - 30 100 0 - 20 - 60 - 140 - 80 - 40 - 100 - 120 typical performance characteristics v rs+ = v rs - = 3.6 v; t a = +25 c, unless otherwise noted. - 40 - 15 35 60 85 10 temperature - c gain error - % v sense - mv v out - v v out vs v sense @ supply = 2v frequency - khz 40 80 1.2 1.8 1.4 1.6 0.5 25 110 0.01 0.001 0.1 1 10 1000 100 0.01 0.4
TS1103 page 6 TS1103ds r1p0 rtfds 200 s/div 200 s/div small - signal pulse response, gain = 100 v sense v out v sense v out typical performance characteristics v rs+ = v rs - = 3.6 v; c out = 0pf; t a = +25 c, unless otherwise noted. 200 s/div 200 s/div small - signal pulse response, gain = 50 v sense v out v sense v out large - signal pulse response, gain = 50 200 s/div 200 s/div small - signal pulse response, gain = 25 v sense v out v sense v out large - signal pulse response, gain = 25 large - signal pulse response, gain = 100
TS1103 TS1103ds r1p0 page 7 rtfds pin functions pin label function 1 gnd ground . connect this pin to analog ground. 2 sign comparator output, push - pull; sign is high for ( v rs+ > v rs - ) and low for ( v rs - > v rs + ). 3 out output voltage. v out is proportional to v sense = ( v rs+ - v rs - ) or ( v rs - - v rs + ). 4 rs - external sense resistor load - side connection 5 vdd s comparator external power supply pin; connect this pin to systems logic vdd supply. 6 rs+ external sense resistor power - side connection block diagram description of operation th e internal configuration of the TS1103 C a bi directional high - side, current - sense amplifier C is a variation of the ts1100 uni - directional current - sense amplifier. in the design of the TS1103 , the input amplifier was reconfigured for fully differential input/output operation and a second low - threshol d p - channel fet (m2) was added where the drain terminal of m2 is also connected to rout. therefore, the behavior of the TS1103 for when v rs - > v rs+ is identical for when v rs+ > v rs - . referring to the typical application circuit on page 1 , the inputs of the TS1103 s differential input/output amplifier are connected across an external rsense resistor that is used to measur e current. at the non - inverting input of the TS1103 (the rs - terminal), the applied voltage is i load x rsense. since the rs - terminal is the non - inverting i nput of the internal op amp, op amp feedback action forces the inverting input of the internal op amp to the same potential (i load x rsense). therefore, the voltage drop across rsense (v sense = v rs+ - v rs - ) and the voltage drop across r gaina (at the rs+ terminal) are equal. necessary for gain ratio match, both r gaina and rgainb are the same value. sin ce p - channel m1s source is connected to the inverting input of the internal op amp and since the voltage drop across r gaina is the same as the
TS1103 page 8 TS1103ds r1p0 rt f ds external v sense , op amp feedback action drives the gate of m1 such that m1 s drain - source current is equal to: ds m 1 v se se r a a or ds m 1 l ad x r se se r a a since m1s drain terminal is connected to rout, the output voltage of the TS1103 at the out terminal is, therefore; v l ad x r se se x r r a a when the voltage at the rs - terminal is greater than the voltage at the rs+ terminal, the external vsense voltag e drop is impressed upon rgainb. t he voltage drop across rgainb is then converted into a current by m2 that then produces an output voltage across rout. in this design, when m1 is conducting current ( v rs+ > v rs - ), the TS1103 s internal amplifier holds m2 off. when m2 is conducting current ( v rs - > v rs + ), the internal amplifier holds m1 off. in either case, the disabled fet does not contribute to the resultant output voltage. the current - sense amplifiers gain accuracy is therefore the ratio match of rout t o r gain[a/b] . for each of the four gain options available, table 1 lists the values for rout and r gain[a/b] . the TS1103 s output stage is protected against input overdrive by use of an output current - limiting circuit of 3ma (typical) and a 7v internal clam p protection circuit . table 1: internal gain setting resistors (typical values) gain (v/v) r gain[a/b] ( ) rout ( ) part number 25 400 10k TS1103 - 25 50 200 10k TS1103 - 50 100 100 10k TS1103 - 100 200 100 20k TS1103 - 200 the sign comparator output as shown in the s1103s block diagram , the design of the TS1103 incorporated one additional feature C an analog comparator the inputs of which monitor the internal amplifiers differential output voltage. while the voltage at the TS1103 s terminal indi cates the magnitude of the load current, the TS1103 s s output indicates the load currents direction. the sign output is a logic high when m1 is conducting current (v rs+ > v rs - ). alternatively, the sign output is a logic low when m2 is conducting curre nt (v rs+ < v rs - ). he s comparators transfer characteristic is illustrated in figure 1. unlike other current - sense amplifiers that implement a out/sign arrangement, the TS1103 exhibits no dead zone at load switchover. figure 1 : TS1103 's sign comparator transfer characteristic. sign propagation delay - ms figure 2 : sign comparator propagation d elay vs v sense . 100 0.1 10 1 v sense ( v rs+ - v rs - ) - mv 0.1 1 10 100
TS1103 TS1103ds r1p0 page 9 rtfds he other attribute of the s comparators behavior is its propagation delay as a function of applied v sense [(v rs+ - v rs - ) or (v rs - - v rs+ )]. as shown in figure , the s comparators propagation delay behavior is symmetric regardless of current - flow direction and is inversely proportional to v sense . applications information choosing the sense resistor selecting the optimal value for the external rsense is based on the following criteria and for each commentary follows: 1) rsense voltage loss 2) v out swing vs. applied input voltage at v rs+ and desired v sense 3) total i load accuracy 4) circuit efficiency and power dissipation 5) rsense kelvin connections 1) rsense voltage loss for lowest ir power dissipation in rsense, the smallest usable resistor value for rsense should be selected. 2) v out swing vs. applied input voltage at v rs+ and desired v sense as there is no separate power supply pin for the TS1103 , the circuit draws its power from the voltage at its rs+ and rs - terminal s . therefore, the signal voltage at the out terminal is bounded by the m inimum voltage applied at the rs+ terminal. therefore, v out(max) = v rs+(min) - v sense(max) C v oh(max) and r se se v max a l ad max where the full - scale v sense should be less than v ou t(max) / a at the applications minimum rs+ terminal voltage. for best performance with a 3.6v power supply, rsense should be chosen to generate a v sense of: a) 120mv (for the 25v/v gain option), b) 60mv (for the 50v/v gain option), c) 30mv (for the 100v/v gain option), or d) 15mv (for the 200v/v gain option ) at the full - scale i load current in each application. for the case where the minimum power supply voltage is higher than 3.6v, each of the four full - scale v sense s above can be increased. 3) total load current accuracy in the TS1103 s linear region where v out < v out(max) , there are two specifications related to the circuits accuracy: a the TS1103 s input offset voltage (v os(max) = 2 00v ) and b) its gain error (ge(max) = 0.6 %). an expression for the TS1103 s total error is given by: v out = [gain x (1 ge) x v sense ] (gain x v os ) a large value for rsense permits the use of smaller load currents to be measured more accurately because the effects of offset voltages are less significant when compared to larger vsense voltages. due car e tho ugh should be exercised as previously mentioned with large values of rsense. 4) circuit efficiency and power dissipation ir losses in rsense can be large especially at high load currents. it is important to select the smallest, usable rsense value to min imize power dissipation and to keep the physical size of rsense small. if the external rsense is allowed to dissipate significant power, then its inherent temperature coefficient may alter its design center value, thereby reducing load current measurement accuracy. precisely because the TS1103 s input stage was designed to exhibit a very low input offset voltage , small rsense values can be used to reduce power dissipation and minimize local hot spots on the pcb. 5) rsense kelvin connections for optimal v sense accuracy in the presence of large load currents, parasitic pcb track resistance should be minimized. kelvin - sense pcb connections between rsense and the TS1103 s rs+ and rs - terminals are strongly recommended. the drawing in figure 3 illustrates the connections between the
TS1103 page 10 TS1103ds r1p0 rt f ds current - sense amplifier and the current - sense resistor. the pcb layout should be balanced and symmetrical to minimize wiring - induced errors. in addition, the pcb layout for rsense should include good thermal management techniques for optimal rsense power dissipation. 6 ) rsense composition current - shunt resistors are available in metal film, metal strip, and wire - wound constructions. wire - wound current - shunt resistors are constructed with wire spirally wound onto a core. as a result, these types of current shunt resistors exhibit the largest self inductance. in applications where the load current contains high - frequency transients, metal film or metal strip cu rrent sense resistors are recommended. internal noise filter in power management and motor control applications, current - sense amplifiers are required to measure load currents accurately in the presence of both externally - generated differential and common - mode noise. an example of differential - mode noise that can ap pear at the inputs of a current - sense amplifier is high - frequency ripple. high - frequency ripple C whether injected into the circuit inductively or capacitively - can produce a differential - mode voltage drop across the external current - shunt resistor (rsens e). an example of externally - generated, common - mode noise is the high - frequency output ripple of a switching regulator that can result in common - mode noise injection into both inputs of a current - sense amplifier. even though the load current signal bandwi dth is dc, the input stage of any current - sense amplifier can rectify unwanted, out - of - band noise that can result in an apparent error voltage at its output. this rectification of noise signals occurs because all amplifier input stages are constructed with transistors that can behave as high - frequency signal detectors in the same way pn - junction diodes were used as rf envelope detectors in early radio designs. against common - mode injected noise, the amplifiers internal common - mode rejection is usually suff icient. to counter the effects of externally - injected noise, it has always been good engineering practice to add external low - pass filters in series with the inputs of a current - sense amplifier. in the design of discrete current - sense amplifiers, resistor s used in the external low - pass filters were incorporated into the circuits overall design so errors because of any input - bias current - generated offset voltage errors and gain errors were compensated. with the advent of monolithic current - sense amplifier s, like the TS1103 , the addition of external low - pass filters in series with the current - sense amplifiers inputs only introduces additional offset voltage and gain errors. to minimize or eliminate altogether the need for external low - pass filters and to m aintain low input offset voltage and gain errors, the TS1103 incorporates a 50 - khz (typ), 2 nd - order differential low - pass filter as shown in the TS1103 s block diagram. output filter capacitor if the TS1103 is part of a signal acquisition system where it s out terminal is connected to the input of an adc with an internal, switched - capacitor track - and - hold circuit, the internal track - and - holds sampling capacitor can cause voltage droop at v out . a 22nf to 100nf good - quality ceramic capacitor from the out te rminal to gnd forms a low - pass filter with the TS1103 s r out and should be used to minimize voltage droop (holding v out constant during the sample interval. using a capacitor on the out terminal will also reduce the TS1103 s small - signal bandwidth as well as band - limiting amplifier noise. pc board layout and power - supply bypassing for optimal circuit performance, the TS1103 should be in very close proximity to the external current - sense resistor and the pcb tracks from rsense to the rs+ and the rs - input terminals of the TS1103 should be short and symmetric. also recommended are a ground plane and surface mount resistors and capacitors. figure 3 : making pcb connections to r s ense.
TS1103 touchstone semiconductor, inc. page 11 630 alder drive, milpitas, ca 95035 TS1103ds r 1p0 +1 (408) 215 - 1220 ? www.touchstonesemi.com rtfds package outline draw ing 6 - pin sot23 package outline drawing (n.b., drawings are not to scale) information furnished by touchstone semiconductor is believed to be accurate and reliable. however, touchstone semiconductor does not assume any responsibility for its use nor for any infringements of patents or other rights of third parties that may result from its use , and all information provided by touchstone semiconductor and its suppliers is provided on an as is basis, without warranty of any kin d . touchstone semicond uctor reserves the right to change product specifications and product descriptions at any time without any advance notice. no license is granted by implication or otherwise under any patent or patent rights of touchstone semiconductor. touchstone semicondu ctor assumes no liability for applications assistance or customer product design. customers are responsible for their product s and applications using touchstone semiconductor components. to minimize the risk associated with customer products and applicatio ns, customers should provide adequate design and operating safeguards. trademarks and registered trademarks are the property of t heir respective owners. 0 ~ 8 n o t e : d i m e n s i o n a r e e x c l u s i v e o f m o l d f l a s h a n d g a t e b u r r . 2 . d i m e n s i o n a r e e x c l u s i v e o f s o l d e r p l a t i n g . 3 . t h e f o o t l e n g t h m e a s u r i n g i s b a s e d o n t h e g a u g e p l a n e m e t h o d . 4 . p a c k a g e i s s u r f a c e t o b e m a t t e f i n i s h v d i 1 1 ~ 1 3 . 5 . d i m e n s i o n s a n d t o l e r a n c e s a r e a s p e r a n s i y 1 4 . 5 m , 1 9 8 2 . 6 . t h i s p a r t i s c o m p l i a n t w i t h e i a j s p e c i f i c a t i o n s c 7 4 a a n d j e d e c m o - 1 7 8 a b s p e c . 7 . d i e i s f a c i n g u p f o r m o l d , d i e i s f a c i n g d o w n f o r t r i m / f o r m , i e . r e v e r s e t r i m / f o r m . 8 . a l l d i m e n s i o n s a r e i n m m . 0 . 0 5 0 ( m i n ) 0 . 1 5 ( m a x ) 0 . 9 0 - 1 . 4 5 1 0 t y p . ( 2 p l c s ) 1 0 t y p . ( 2 p l c s ) 0 . 6 0 - 0 . 8 0 1 0 t y p . ( 2 p l c s ) 0 . 0 9 C 0 . 1 2 7 1 . 5 0 C 1 . 7 5 0 . 2 5 g u a g e p l a n e 0 . 3 0 - 0 . 5 5 1 0 t y p . ( 2 p l c s ) 0 . 5 0 - 0 . 7 0 2 . 8 0 - 3 . 0 0 0 . 9 5 0 0 . 9 5 0 t y p . t y p . 2 . 6 0 - 3 . 0 0 1 . 5 0 - 1 . 7 5 0 . 3 0 0 ( m i n ) 0 . 5 0 0 ( m a x )

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